Basic Low Power techniques to reduce Power[转]

From:http://socdesignsource.org/magicbluesmoke/?p=32

By  gmaben

 

In the process of finding all the advanced techniques to reduce power, we tend to ignore the basic techniques available with the majority of EDA tools. Some of these techniques that are available today and can reduce power to a great extent are :-

(1) Clock gating
(2) Sizing
(3) Factoring
(4) Pin swapping
(5) Inversion Push
(6) Low Power Placement
(7) Register Clustering
(8) Low Power CTS to reduce power in the clock tree
(9) Multi-Vt Optimization to minimize usage of Low Vt cells
(10) Operand Isolation
(11) Data Gating
(12) Bubble Algorithm

These techniques can be enabled by turning on some switches/variables in the Implementation tools. Most of these techniques require representative vector-set. Identifying good representative vectors is a real challenge.

If the vectors are very difficult to access, the best bet would be to enable these techniques once your design meets the required timing/area goals.

We can definitely get an estimate on the average activity factor of various blocks of the design and use these factors to enable low power optimization. This approach can help us in saving power to quite an extent.

For example, I have seen in one of the recent activities, we were able to get around 15-20% power reduction just by enabling Low Power Placement.