Wire Load Model

Defining Wire Load Models
    Wire load modeling allows you to estimate the effect of wire length and fanout on the resistance, capacitance, and area of nets. Design Compiler uses these physical values to calculate wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on statistical information specific to the vendors' process. The models
include coefficients for area, capacitance, and resistance per unit length, and a fanout-to-length table for estimating net lengths (the number of fanouts determines a nominal length).
Note:
You can also develop custom wire load models.

 

Wire load models estimate the effect of wire length on design performance. It should be speicfied when define the design environment.

 

Determining Available Wire Load Models

Use the report_lib command to list the wire load models defined in a technology library. The library must be loaded in memory before you run the report_lib command.

eg:

dc_shell-xg-t> read_file my_lib.db

 

Example   Wire Load Models Report
****************************************
Report : library
Library: my_lib
Version: Y-2006.06
Date : Mon May 1 10:56:49 2006
****************************************
...
Wire Loading Model:
Name : 05x05
Location : my_lib
Resistance : 0
Capacitance : 1
Area : 0
Slope : 0.186
Fanout Length Points Average Cap Std Deviation
------------------------------------------------------------------------
1  0.39

 

Name : 10x10
Location : my_lib
Resistance : 0
Capacitance : 1
Area : 0
Slope : 0.311
Fanout Length Points Average Cap Std Deviation
------------------------------------------------------------------------
1 0.53

...

 

Specifying Wire Load Models and Modes

The default_wire_load library attribute identifies the default wire load model for a technology library.To change the wire load model or mode specified in a technology library, use the set_wire_load_model and set_wire_load_mode commands.

eg:

dc_shell-xg-t> set_wire_load_model "10x10"

dc_shell-xg-t> set_wire_load_mode enclosed

 

If you need more detail infomation about wire_load_model,please refer the Design Compiler Usage.