Question:
I have a pulse-shaping circuit similar to the one shown in the following figure.
In the following circuit, only the falling edge from and1/A and rising edge from
and1/B should be used (see waveforms).
How should this be modelled in PrimeTime?
Answer:
This can be done using the set_case_analysis command and assigning values "falling"
to and1/A and "rising" for and1/B. A sample verilog netlist, a set of constraint
and the timing reports are shown below to demonstrate the behaviour.
//Verilog netlist
module clock_shape (in,out);
input in;
output out;
buf1a1 b1 (.A(in), .Y(u1_out));
buf1a1 b2 (.A(u1_out), .Y(u2_out));
buf1a1 b3 (.A(u2_out), .Y(u3_out));
and2a1 and1 (.A(in), .B(u3_out),.Y(out));
endmodule
#Constraints
create_clock -p 1 -name clk
set_input_delay -clock clk 0 [all_inputs]
set_output_delay -clock clk 0 [all_outputs]
set_case_analysis falling [get_pin and1/A]
set_case_analysis rising [get_pin and1/B]
report_timing -input_pins -fall_to out
report_timing -input_pins -rise_to out
report_timing -input_pins -through and1/A -fall_to out
#Reports
pt_shell> report_timing -input_pins -fall_to out
****************************************
Report : timing
-path_type full
-delay_type max
-input_pins
-max_paths 1
Design : clock_shape
Version: Z-2007.06-SP2
Date : Thu Oct 4 16:03:46 2007
****************************************
Startpoint: in (input port clocked by clk)
Endpoint: out (output port clocked by clk)
Path Group: clk
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 f
in (in) 0.00 0.00 f
and1/A (and2a1) 0.00 0.00 f
and1/Y (and2a1) 0.12 0.12 f
out (out) 0.00 0.12 f
data arrival time 0.12
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
output external delay 0.00 1.00
data required time 1.00
---------------------------------------------------------------
data required time 1.00
data arrival time -0.12
---------------------------------------------------------------
slack (MET) 0.88
1
pt_shell> report_timing -input_pins -rise_to out
****************************************
Report : timing
-path_type full
-delay_type max
-input_pins
-max_paths 1
Design : clock_shape
Version: Z-2007.06-SP2
Date : Thu Oct 4 16:04:25 2007
****************************************
Startpoint: in (input port clocked by clk)
Endpoint: out (output port clocked by clk)
Path Group: clk
Path Type: max
Point Incr Path
---------------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
in (in) 0.00 0.00 r
b1/A (buf1a1) 0.00 0.00 r
b1/Y (buf1a1) 0.14 0.14 r
b2/A (buf1a1) 0.00 0.14 r
b2/Y (buf1a1) 0.18 0.32 r
b3/A (buf1a1) 0.00 0.32 r
b3/Y (buf1a1) 0.18 0.50 r
and1/B (and2a1) 0.00 0.50 r
and1/Y (and2a1) 0.18 0.68 r
out (out) 0.00 0.68 r
data arrival time 0.68
clock clk (rise edge) 1.00 1.00
clock network delay (ideal) 0.00 1.00
output external delay 0.00 1.00
data required time 1.00
---------------------------------------------------------------
data required time 1.00
data arrival time -0.68
---------------------------------------------------------------
slack (MET) 0.32
1
pt_shell> report_timing -input_pins -through and1/A -rise_to out
****************************************
Report : timing
-path_type full
-delay_type max
-input_pins
-max_paths 1
Design : clock_shape
Version: Z-2007.06-SP2
Date : Thu Oct 4 16:04:57 2007
****************************************
No constrained paths.
1
Labels: AsicDesign, Script
