Some White Paper for Low-Power

Low-Power Resources

Whitepaper — "Power Consumption in 65 nm FPGAs"  With the introduction of the Xilinx™-5 family, Xilinx is...    Read more

Whitepaper — "Power Management In Complex SoC Design"  The rise in SoC size and speed, as well as the increase in...    Read more

Whitepaper — "Power Integrity for SoCs: Power Planning and Signoff Flows"  Power integrity has become a crucial part of...    Read more

Whitepaper — "A Practical Methodology for Calculating Acceptable IR Drop Targets in Advanced VDSM Design"   
Smaller process geometries have led to a dramatic increase in...    Read more

Basic Low Power techniques to reduce Power[转]

From:http://socdesignsource.org/magicbluesmoke/?p=32

By  gmaben

 

In the process of finding all the advanced techniques to reduce power, we tend to ignore the basic techniques available with the majority of EDA tools. Some of these techniques that are available today and can reduce power to a great extent are :-

(1) Clock gating
(2) Sizing
(3) Factoring
(4) Pin swapping
(5) Inversion Push
(6) Low Power Placement
(7) Register Clustering
(8) Low Power CTS to reduce power in the clock tree
(9) Multi-Vt Optimization to minimize usage of Low Vt cells
(10) Operand Isolation
(11) Data Gating
(12) Bubble Algorithm

These techniques can be enabled by turning on some switches/variables in the Implementation tools. Most of these techniques require representative vector-set. Identifying good representative vectors is a real challenge.

If the vectors are very difficult to access, the best bet would be to enable these techniques once your design meets the required timing/area goals.

We can definitely get an estimate on the average activity factor of various blocks of the design and use these factors to enable low power optimization. This approach can help us in saving power to quite an extent.

For example, I have seen in one of the recent activities, we were able to get around 15-20% power reduction just by enabling Low Power Placement.

ECO小错

问题：

在定义wire的时候，信号名中带"\"，如wire  \CNT[0] ;

不知道是公司的Naming Rule规定的还是Verilog语法规定，在此类信号名的前后必须有一个空格。

但我通过手工输入Command的方式产生的Netlist是不符合这规定的，因此很可能是公司Naming Rule定的。

结论：

在做ECO时手动修改的那部分Netlist一定得符合设计的Naming Rule，此类检查可以通过Debussy的语法检查发现。