给数字IC设计新手入门的几点建议

1.概念性的东西一点要弄明白，如一些基本的名词，简称等，养成搜索的习惯，通过这些关键字，慢慢就熟悉整个行业。 建议碰到不熟悉的关键字，通过google，不但查到该词的意思，更要看与该词相关的一些内容。另外，给一个常用的查简称的网站， http://www.thefreedictionary.com/  ，我常用的办法是用"简称 + stand for"在google中搜索，一般最匹配的结果就是上面那个网站给的。

2.学习基本的HDL语言，FPGA设计流程和ASIC设计流程。做数字的话用HDL语言就好比建房子时的垒砖头，那些设计流程就好比按照房子的框架把砖头垒满，构成一间间的房屋。会了这几个东西就你就好比成了一个泥水匠。也许有人说建筑师不一定得从泥水匠开始做起，在现代社会分工这么明确，确实如此。不过我认为只有对底层的砖头的性能了解更清楚，才能造出最佳性能飞房屋。其中对于HDL语言的学习，建议避免深究各种语法，一切以实用为主，多看看人家的示例，如 opencores上面的，当你对常用的这些语法都很熟悉了之后，如果需要某些复杂的写法，翻翻书也很容易上手。对于设计流程的学习，本人的观点是不但要知其然，更要知其所以然。那样才能对设计流程更好地掌握，更进一步来优化设计流程。如对某个步骤的做法，实现原理，EDA工具的实现方法等。

3.注重知识面的扩展。IC设计是个大杂烩，知识面一定要广。平时多看看各种协议，标准，甚至是和IC看起来毫无关系的东西，人类的知识体系在各科之间有着一定的联系，看多了就容易触类旁通了。

4.对EDA工具的学习，看文档，实践，两者可谓相辅相成。动辄几百上千页的英文文档要看得很明白也不是件容易的事情。不过一般来说，文档都有个简单的tutorial之类的，就是工具的指南，这部分一般都是讲工具的入门，可以边看边用边思考。个人觉得一个工具入门容易，但要用好它就需要点功夫了。另外，对于大多数在校学生来说，没有Unix/Linux/Sun的EDA环境来学习，而且个人要装这些工具也比较麻烦。建议正在学习的同学们发扬点开创精神，辛苦一点，搭建这样一个平台，留给师弟师妹们，这样一代一代才会进步。 51EDA的FTP上有不少EDA工具，多上上他的论坛，就可以上ftp了，也能学习到一些工具的安装方法。

5.多关注新技术，这样才能让自己拥有可持续的竞争力。

How To Find All The High Fanout Nets In PrimeTime

set high_fanout 2

set gan [get_nets -h *]

foreach_in_collection gg $gan {

   set ggname [get_attribute $gg full_name]

   # echo "Processing $ggname"

   set gpins [get_pins -leaf -quiet -of $gg]

   set gpins_in [filter_collection $gpins "direction==in"]

   set gpins_in_soc [sizeof_collection $gpins_in]

   if { $gpins_in_soc > $high_fanout } {

 echo "Net $ggname is a high fanout net $gpins_in_soc greater than $high_fanout connections"

   }
}

Handle Unconnected Pins in Design Compiler

Question:

The original Verilog code snippet is as follows:
module sub ( C, z );
input C;
output z;
AN3 U1 ( .A(), .B(), .C(C), .Z(z) );
endmodule
In the dumped Verilog, the code is as follows:
module sub ( C, z );
input C;
output z;
AN3 U1 ( .A(1'b0), .B(1'b0), .C(C), .Z(z) );
endmodule
Why does Design Compiler connect unconnected pins to 0?

Answer:

Because Design Compiler does not allow a floating input of a cell, an
unconnected input will always be tied to '0' or '1'.
So in the dumped Verilog, you can see the unconnected pin A connected to 0,
But from version Z-2007.03-SP1, the behavior is different. Check the dumped
Verilog; it is similar to the following:
=============================
wire net1, net2;
MUX2D1 U1 ( .I0(net1), .I1(net2),.C(C), .Z(z) );
Notice the difference in the generated Verilog between versions
Y-2006.06 and Z-2007.03.

Wire Load Model

Defining Wire Load Models
    Wire load modeling allows you to estimate the effect of wire length and fanout on the resistance, capacitance, and area of nets. Design Compiler uses these physical values to calculate wire delays and circuit speeds. Semiconductor vendors develop wire load models, based on statistical information specific to the vendors' process. The models
include coefficients for area, capacitance, and resistance per unit length, and a fanout-to-length table for estimating net lengths (the number of fanouts determines a nominal length).
Note:
You can also develop custom wire load models.

 

Wire load models estimate the effect of wire length on design performance. It should be speicfied when define the design environment.

 

Determining Available Wire Load Models

Use the report_lib command to list the wire load models defined in a technology library. The library must be loaded in memory before you run the report_lib command.

eg:

dc_shell-xg-t> read_file my_lib.db

 

Example   Wire Load Models Report
****************************************
Report : library
Library: my_lib
Version: Y-2006.06
Date : Mon May 1 10:56:49 2006
****************************************
...
Wire Loading Model:
Name : 05x05
Location : my_lib
Resistance : 0
Capacitance : 1
Area : 0
Slope : 0.186
Fanout Length Points Average Cap Std Deviation
------------------------------------------------------------------------
1  0.39

 

Name : 10x10
Location : my_lib
Resistance : 0
Capacitance : 1
Area : 0
Slope : 0.311
Fanout Length Points Average Cap Std Deviation
------------------------------------------------------------------------
1 0.53

...

 

Specifying Wire Load Models and Modes

The default_wire_load library attribute identifies the default wire load model for a technology library.To change the wire load model or mode specified in a technology library, use the set_wire_load_model and set_wire_load_mode commands.

eg:

dc_shell-xg-t> set_wire_load_model "10x10"

dc_shell-xg-t> set_wire_load_mode enclosed

 

If you need more detail infomation about wire_load_model,please refer the Design Compiler Usage.

Why we should do gate-level simulation?[转]

From http://blog.dicder.com/html/3/3-287.html

SNUG:All My X's Come From Texas…Not!!
Matt Weber
Jason Pecor
Silicon Logic Engineering
In a recent ESNUG article ( http://www.deepchip.com/items/0421-01.html), eighteen engineers shared their view of the current usefulness of gate level simulation. Only one of those engineers  has completely removed gate level simulation from their design flow. The other engineers listed  many reasons for continuing to do some level of gate level simulation.
1. Since scan and other test structures are added during and after synthesis, they are not checked by the rtl simulations and therefore need to be verified by gate level simulation.
2. Static timing analysis tools do not check asynchronous interfaces, so gate level simulation is required to look at the timing of these interfaces.
3. Careless wildcards in the static timing constraints set false path or mutlicycle path constraints where they don't belong.
4. Design changes, typos, or misunderstanding of the design can lead to incorrect false paths or multicycle paths in the static timing constraints.
5. Using create_clock instead of create_generated_clock leads to incorrect static timing between clock domains.
6. Gate level simulation can be used to collect switching factor data for power estimation.
7. X's in RTL simulation can be optimistic or pessimistic. The best way to verify that the design does not have any unintended dependence on initial conditions is to run gate level simulation.
8. It's a nice "warm fuzzy" that the design has been implemented correctly.

 

A IPcore Introduction[just as a template]

BodaHx8 - MPEG-2 MP + H.264 HP + VC-1 AP + MPEG-4 ASP (DivX) + RV8/9/10 + JPEG codec (1920*1080*30)

Overview

     Chips&Media's BodaHx8 is a high-performance and optimally-unified multi-standard decoder IP that performs three major decoding functionalities such as H.264, MPEG-2, MPEG-4 (DivX), RV8/9/10, JPEG codec and VC-1 up to HD resolution at 30 frames per second. Under our technologies, BodaHx8 needs ultra low-power and ultra low clock frequency based on Chips&Media's advanced video decoding hardware architecture, while BodaHx8 provides decent flexibility in error concealment, error resilient, and multi-resolution/multiplex decoder control based on exclusively designed video core processor.

Features

Standards Compliance - decoder only

ISO/IEC 14496-10 AVC BP@L4, MP@L4 ,HP@L4.1

ISO/IEC 13818-2 MPEG-2 MP@HL

ISO/IEC 14496-2 MPEG-4 ASP (DivX)

SMPTE VC-1 SP, MP, AP@L3

RV8/9/10

JPEG

Benefits

Interface

Host interface: AMBA3 32-bit APB interface

External memory interface: AMBA3 64-bit AXI Interface or AMBA2 AHB interface

Customized interface for optimally designed bus multi-master environments can be available

Decoding tools

Support all features of the standards

Deblocking filter for post-processing

State-of-art error concealment strategy

Simultaneous multi-standard/multiple decoding is possible

Error resilience tools

Optional: Built-in rotation/mirroring function to remove redundant bus-loading: 90 x n degree rotation (n=0,1,2,3); Vertical/horizontal mirroring

Performance

HD(1920X1080) decoding @ 150MHz

Required host processor resource to run: less than 1 MIPS

Deliverables

RTL source code

IP integration guide & user guide

Test-bench

Evaluation Board

Tech Specs

Part Number	BodaHx8
Short description	MPEG-2 MP + H.264 HP + VC-1 AP + MPEG-4 ASP (DivX) + RV8/9/10 + JPEG codec (1920*1080*30)
Provider:	Chips&Media, Inc
Portability	FPGA
ASIC Target	TSMC@90um
FPGA Target	Xilinx Virtex 4
Type	Soft
Compliant Standard	MPEG-2 MP@HL / MPEG-4 ASP (DivX) / H.264 HP@L4.1 / VC-1 AP@L3.0 / RV8/9/10 / JPEG codec (Full HD decoder)
Maturity	Very good
Availability	Oct, 2007
TSMC Rating :	Verification: 0.09G (CLN90G)
FPGA Technology:	Xilinx: Virtex-4 LX
Bus Compliance :	AMBA AXI

Datasheet:
Related Links:

Try to embbed a video from YouTube

Just For Test~~~

How Do I Preserve MUX Structures in the Netlist?[from solvnet]

[I think it's very useful!]
How Do I Preserve MUX Structures in the Netlist?

Question:

I know that I can map the "full case" statements in RTL to MUX_OP synthetic components by using the "infer_mux" synthesis pragma or the "hdlin_infer_mux" global variable. However, in some cases I see that these MUX_OPs are inferred in the GTECH but mapped to non-MUX random logic gates in the library after compile or compile_ultra. How can I preserve these MUX structures even if the QOR is degraded with library MUX cells?

Answer:

If you want Design Compiler to preferentially map multiplexing logic to multiplexers or multiplexer trees in your technology library, you must infer MUX_OP cells. But it doesn't guarantee that the tool will use the MUX from the target library in the final implementation after compile or compile_ultra. Keep in mind that forcing MUXes might degrade the QOR of your design in some cases. So Design Compiler can change MUX_OPs to random logic based on the constraints. Starting from version Z-2007.03-SP3, you can use the set_size_only or set_map_only commands to set size_only or map_only attributes on the MUX_OP cells as follows: -Without size_only and map_only attributes, the MUX_OP synthetic cells are mapped to MUX cells if both area and delay are comparable to equivalent combinational random logic; otherwise combinational random logic is used. -With the map_only attribute, the MUX_OP is initially mapped to MUX cells, but are remapped to combinational random logic if delay can be improved; -With the size_only attribute, the MUX_OP is mapped to MUX cells. The size_only restricts optimization and can result in worse QOR. For example, you can set the attributes as one of the following: set_size_only [get_cells -hier * -filter "@ref_name =~ *MUX_OP*"] or set_map_only [get_cells -hier * -filter "@ref_name =~ *MUX_OP*"] Note: The "set_size_only" solution does not work in versions earlier to Z-2007.03-SP3. The "set_map_only" solution does not work in version earlier to Z-2007.03-SP2.

A good blog for fpga

FPGA design from scratch

http://svenand.blogdrive.com/