Query Yourself before Architecting a Chip

[From:http://www.vlsichipdesign.com/askyourselfarchitect.html]
This article assuming you are an Architect and What all questions will come to your thought process before Architecting and making the Chip as a first-pass success. Chip Design is an Integration Challenge.

1. What is the targetted market for this Chip.
2. What are the competitor's to this Chip and Market Requirement and ROI
3. What is the Fabrication Unit the Chip is targetted for?
4. What is the Success rate and Yield numbers achieved in the Fabrication Unit
5. What is the technology Process targetted for
6. What is the correlation of the library models w.r.t. Silicon
7. What are the various Protocols the Chip is going to address
8. Hardware & Software Parti-tioning.
9. What is the processor/micro-controller suitable for this application.
10. What is the bus-architecture targetted
11. What is the performance targets for this bus architecture
12. What are the various Interfaces the Chip is having
13. Is the design going to be in single Vt or with Multi-Vt design
14. Is using Embedded macro's right choice or Memory Macros
15. What are the IP's are going to be Re-usued
16. What are the IP's going to Hard-macro's
17. What is the Verification Status and corner-case coverage of the I.P's
18. What is the Die-size targetted/Estimated for the Chip
19. What is the Power targets
20. Is Power Management Unit a requirement in the chip to reduce Dynamic power
21. What are the mechanisms followed to reduce the leakage power
22. Is Module enables/clock-gating a part of the Methodology
23. Is resets going to synchronous or asynchronous
24. What are the various Synchronous Mechanisms for data-transfer's
25. How many clock-domains required for the Chip
26. How many PLL's are required or single PLL sufficient for all the clocks required
27. What is the thought process behind PAD's Is LVTTL/SSTL pads
28. Is the package going to wire-bond or Flip-chip
29. Methodology for Optimal Power-grid design
30. What are the noise reducing Mechanism's in case of analog integration
31. Is there any requirement of speed monitor's or process checking blocks
32. What is the type of fuses used laser fuse or efuses
33. Is there any requirement of Fib Cells in the Design
34. What are the mechanism's used to handle ESD
35. what is the reliability target of the Chip and how it is addressed
36. What are the Mechanisms used for Yield improvement
37. Is the chip tested at at-speed test
38. How much Memory-map is allocated for the IP's
39. What is the metric for spare-gates in the Chip for ECO's
40. Is repairable memories required
41. What is the tester targetted and the requirement to the Chip in terms of Scan-chain
42. Is test-vector compression mechanism's a requirement
43. What is the PLL performance in terms of Jitter
44. What is the Interrupt handling mechanism with in the Chip.
45. What is the ROM-Code for the Chip.
46. What is the Chip utilization targets
47. Will the chip be routable or any requirement for special libraries with different routing tracks.
48. What is the Methodology for tools and versions
49. What is the Version control mechanism planned for data handling across multi Geographical Environments.
50. What is the signoff criteria for the Chip
51. What is the frequency targets for the Chip.
52. Is there room for further revisions of the Chip.
53. If the Chip has DDR/SDR interface is there any requirement for DLL.
54. What are the limitations of the Tools interms of Complexity/run-times/turn-around times/Computation Power requirements.
55. What is the Mechanisms/Steps taken for the various Variabilities in the Chip IR drop/Power ground noise/inductance effects/EMI noise/Package noise/Crosstalk noise/Simultaneous Switching noise/Channel length variation/On chip Variation/Inter die variations/Intra die Process variations.

On-Chip Variation(OCV) Analysis

On Chip Variations or inter-die variations could be caused due to :

  • IR drop

  • Vt variations

  • Channel length variation

So the normal flow of qualifying the Timing with plain worst and best corners is no more enough.

 

Performing On-Chip Variation Analysis[From PrimeTime UG]
      To perform on-chip variation analysis, use the set_operating_conditions command.
      Because on-chip variations consider that cells and nets can operate at slightly different operating conditions, you must consider a minimum value and a maximum value for each delay of the design.Specify two operating conditions to represent the lower and upper bounds of the operating condition for on-chip variation, keeping the following guidelines in mind.
• Each delay of the design has an uncertainty bounded by the minimum value (computed for the minimum operating condition) and maximum value (computed for the maximum operating condition).
• Minimum paths are computed using the delay of the minimum operating condition.
• Maximum paths are computed using the delay of the maximum operating condition.

Example 1
This command sequence performs timing analysis for on-chip variation 20 percent below the worst-case commercial (WCCOM)
operating condition. It also performs clock reconvergence pessimism removal for paths with positive slack.
pt_shell> set_operating_conditions -analysis_type on_chip_variation WCCOM
pt_shell> set_timing_derate -min 0.8 -max 1.0

pt_shell> report_timing -remove_clock_reconvergence_pessimism 0.0
Example 2
This command sequence performs timing analysis for on-chip variation between two predefined operating conditions:WCCOM_scaled andWCCOM.It also performsclock reconvergence pessimism removal for paths with slack less than 0.4 ns.
pt_shell> set_operating_conditions -analysis_type on_chip_variation \
              ? -min WCCOM_scaled -max WCCOM
pt_shell> report_timing -remove_clock_reconvergence_pessimism 0.4
Example 3
This command sequence performs timing analysis for on-chip variation 5 percent above and 10 percent below the SDF backannotated
cell delays. For net delays, the on-chip variation is between 2 percent above and 4 percent belowtheSDFback-annotated values.
For timing delays, the on-chip variation for timing checks is 10 percent above the SDF values for setup and 20 percent belowthe SDF values for hold checks.
pt_shell> read_sdf -analysis_type on_chip_variation my_design.sdf
pt_shell> set_timing_derate -cell -min 0.90 -max 1.05
pt_shell> set_timing_derate -net -min 0.96 -max 1.02
pt_shell> set_timing_derate -cell_check -min 0.80 -max 1.10

 

 

Synopsys Design Compiler-A quick Tutorial

From: http://www.vlsiip.com/dc_shell/

Step 0. Invoke Design Compiler
            unix> dc_shell-t
Step 1. Setup technology library. To synthesize a design you need technology library which will contain
       description of the cells from the fab, and their timing. This is usually a .db file found in
       library installation directory. To do this
     1(a). Tell synopsys where your <library>.db file is.
           set search_path {/homes/amittal/s5/work/physical_lib/corelib/tsmc_090_g_art}
     1(b). Tell synopsys what is your technology library, which you want to map your design on called
           set target_library {scadv_tsmc_cln90g_lvt_ss_0p9v_125c.db}
     1(c). Set up link libraries. This is optional .db files which are pre synthesized and ready to be read in
     For this, append your search path where your optional .db files are
           lappend search_path {[exec pwd]}
           lappend search_path {.}
     1(d). Set up link libraries. This is optional .db files which are pre synthesized and ready to be read in
           set link_library  {PLL10CCMID_W_125_1.35.db}
Step 2. Read In your design files
     2(a). if it is verilog:
           read_verilog counter.v
     2(b). if it is vhdl: As it is in this tutorial
           read_vhdl counter.vhd
           read_vhdl counter_top.vhd
     2(c). if it is ddc:
           read_ddc counter.ddc
Step 3. Set Design Constraints:
     3(a) Set frequency of operation: You have to create a clock in the design,
     With a given timeperiod. The command below creates a clock and calls it
     'design_clk' with a timeperiod of 10 ns, (100MHz), and maps it to the
      'clk' input of the design.
           create_clock -period 10 -name design_clk clk
     3(b) Set input constraints : Set how much time would be spent by
     signals arriving into your design, outside your design with respect to the clock
           set_input_delay 4.0 [remove_from_collection [all_inputs ] clk] -clock design_clk
     3(c) Set output constraints : Set how much time would be spent by
     signals leaving your desing, outside your design, before they are captured by
     the same clock
           set_output_delay 7.0 [all_outputs] -clock design_clk
     3(d) Set area constraints : set maximum allowed area to 0 :). well its just to
     instruct design compiler that use as less area as possible.
           set_max_area 0
Step 4. Enable clock gating for low power (optional)
     4(a) The following commands will try to insert clock gates for each 2 registers
           set_clock_gating_style -minimum_bitwidth 2
Step 5. Write formal verification setupfile (optional)
           set_svf -append "counter.svf"
Step 6. Set Register optimization veriables (optional)
     (a) Set automatic removal of constant flipflop(s)
           set compile_seqmap_propagate_constants true
     (b) Set automatic removal of unloaded flipflop(s)
           set compile_delete_unloaded_sequential_cells false
Step 7. Set mapping of sync resets to aviod Xs in sims (optional)
           set hdlin_ff_always_sync_set_reset "true"
Step 8. Set the name of top level as current design and compile the design
     (a)  current_design counter_top
           compile -map_effort high
     (b) If you are using dc ultra :
           compile_ultra
           You may want to turn off output inversion of sequential cells
           compile_ultra -no_seq_output_inversion
Step 9. Write design output netlist
     9(a).Write output in ddc format
           write -format ddc -output counter.ddc -hier
     9(b).Write output in verilog format 
           write -format ddc -output counter.vlog -hier
Step 10. You may want to flatten your design before writing out netlist
           ungroup -all -flatten
           write -format verilog -output counter_flat.vlog
Step 11. Writing a timing report of your design
           report_timing > counter_timing.rep
Step 12. Quit Design Compiler
           quit

 

More random DC shell Tcl mode Commands:

define_design_lib lib1 -path ~/misc/vhdl
analyze -library lib1 -format vhdl /homes/amittal/misc/vhdl/xx.vhdl
get_design_lib_path SYNTH
get_design_lib_path work

read_verilog mse.v

report_timing -delay max -from ARRAYCACHE_I/CACHEDIRRAM_I/regfile64x704_assembly_0/RA_ram[3] -to pCacheMemReqFifoDataOut

report_timing -delay max -through  [find net ARRAYCACHE_I/CACHEDIRRAM_I/regfile64x704_assembly_0/RA_ram[3]]

report_constraint -verbose -all_violators

create_clock -name "myclk" -period 13 [get_ports pClk]

set_output_delay 1.0 -clock [get_clocks myclk]  pCacheMemReqFifoDataOut[161]

set_wire_load_mode segmented

set_wire_load_mode enclosed

update_timing

report_timing -from [find pin ARRAYCACHE_I/LatencyReqReg*/Q] -to pCacheMemReqFifoDataOut

report_timing -from [find pin ARRAYCACHE_I/CACHE_DATA_RAM/DO*] -to pCacheMemReqFifoDataOut

set_output_delay 1.0 -clock myclk pCacheMemReqFifoDataOut

set_false_path -through [find pin ARRAYCACHE_I/FracSetReg*/*]index

It is to be noted that if there are no constraints, 'set_false_path' does not actually works.

I tried to find delays to a output port, without any constraints, form a known point in the design.
I got that.
Then I wanted to find next worst path to that output port, to I set a false path on the path found above.
But it wouldn't work
I then created a clcok and constrainted the output port,
!! False path worked.... magic :)

create_clock -period 4.8 -name vclk
set_input_delay 2.5 pDmaReadRegIndex -clock vclk -add_delay
set_output_delay 2.5 pInsertNopOut -clock vclk -add_delay
set_false_path -from vclk -to PESWITCH_pClk
set_false_path -from PESWITCH_pClk -to vclk
set_false_path -from PESWITCH_pClk -through pDmaReadRegIndex -to pInsertNopOut
report_timing -from pDmaReadRegIndex -to pInsertNopOut

set_input_delay [expr 0.35*$vclk_period] [all_inputs] -clock vclk -add_delay
set_output_delay [expr 0.35*$vclk_period] [all_outputs] -clock vclk -add_delay
set_false_path -from PESWITCH_pClk -through [all_inputs] -to [all_outputs]


set compile_log_format "%elap_time %area %wns %tns %drc %endpoint %group_path"
 

How to Get the Number of Gates in Design Compiler Synthesized Design

set a 2-input NAND gate has an area of 1.

dc_shell> get_attribute { tech_lib_name/2input_nand_gate_name } area